Negedge => posedge or posedge => negedge path. Basically, half cycle sequential paths.

Clock jitter -> PLL circuits -> higher freq, higher jitter -> lower freq, lower uncertainty -> improve the hold slack

I tried to look into it, I dont see any scenario in which hold would be fixed by lowering frequency, unless any of the derates are functional to the frequency.

Reducing the voltage would make the devices slower and help fix hold violations. Reduce the frequency along with voltage to make sure that there are no setup violations because of the slower devices.