Synopsys Applications Engineer interview questions

There were 2 rounds of test due to more number of students, both related to digital electronics, basic CMOS and screening interview happened in same day, based on some basic concepts.

Questions on Verilog, Digital design flow and systemverilog were asked. Attended 3 rounds of technical interviews and one managerial round. Question was to design an FSM with 5 different states using JK flipflops. System verilog basics such as program vs module, fork-join, questions were asked. Interviewer was friendly and helpful