- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
This was the main interview question. Design subroutine (pseduo code) that takes variable length of array whose element are in consecutive order but has one missing element. And minimum length of array should be 2. First and Last element can't be missing
Possible solution vectors to meet set up timing
FIFO design
How to implement not with nand/nor gates
muxs verilog
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Write the verilog code for a counter then change reset to asychronized.
Constraint randomization based question linking to AXI and memory filling
First of all, he asked about the project you have done. Then he asked me two problems related to probability and static. One is to calculate the pdf of the random variable which is function of a set of iid random variables, the other is to derive the MAP for given random variable with specific distribution.
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