1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
Q.There was a discussion on mealy and moore machine.
The first interview asked basic technical questions about logic design, STA and FSM etc. The second one was RTL coding for synchronous FIFO with depth=5
muxs verilog
Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.
Explain past work experience and Project details.
First of all, he asked about the project you have done. Then he asked me two problems related to probability and static. One is to calculate the pdf of the random variable which is function of a set of iid random variables, the other is to derive the MAP for given random variable with specific distribution.
1. How you will verify a block or any module that you designed? 2. Design divide by 3 counters with waveform? 3. Round robin arbitration logic? 4. Sequence detector (overlapping and nonoverlapping)? 5. Verilog code for synchronous and asynchronous flip-flop? 6. CMOS inverter circuit diagram and characteristics? 7. Ring inverter circuit and working? 8. Frequency of oscillations of ring oscillator? 9. Reset synchronizer circuit and working with waveform? 10. AHB Protocol working with waveforms? 11. Problem on Multi-cycle path? 12. Different ways of Synthesis optimization? 13. Identify the components that are consuming power in circuit? 14. How to save power in such power consuming block? 15. Dynamic power consumption formula? 16. Low power RTL coding styles?
Describe a time when you need to gather information from different sources to troubleshoot an issue.
Write verilog code for D ff.
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