how to overcome setup time and hold time violation
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
All the problems are quite common . But some C program questions , such ass what is interrupt
Why do you want to join eInfochips
Design AND gate with 2:1 mux
How will you verify a memory mapped interface with one port?
How do you implement the analog components of a PLL which are non-synthesizable in verilog?
Q: ASIC flow? Q: Hands - on code ; RTL
As per company rules can't tell you,
Questions on verilog, Perl, I2C protocol, Verification plan, Multiplexer
What is cmos. Realization of gates using cmos and gates using mux. Demultiplexer?
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