What is crosstalk delay and how to fix?
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
design a state machine and write Verilog code.
Basic questions related to System Verilog and UVM
Tell some of applications of buffer?
Difference asic/fpga
Write a verilog code to detect the pattern 1011
What’s the difference between direct-mapping and set-associate?
Experience in circuit design and simulation
Design a Neural Network for a system.
1. Memory design and block diagram 2.Verilog programming 3.C++ (oops concepts) 4.SV & UVM components
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