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Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
tell me about your past experience
What is the relationship between read and write clock for different data widths in a FIFO?
Design a level shifter
SystemVerilog vs Verilog
SV UVM APB AXI AHB
Related to SV + UVM + Puzzles + Perl and other scripting language
String manipulation in C++ to take out certain characters.
Given a disc, half of it is white and another one is black, describe how would you detect if it goes clockwise or counterclockwise, and design a digital circuit that would accomplish it.
Truth table of a simple verilog module. blocking/unblocking assignment
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