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1,316 asic engineer interview questions shared by candidates

1. How you will verify a block or any module that you designed? 2. Design divide by 3 counters with waveform? 3. Round robin arbitration logic? 4. Sequence detector (overlapping and nonoverlapping)? 5. Verilog code for synchronous and asynchronous flip-flop? 6. CMOS inverter circuit diagram and characteristics? 7. Ring inverter circuit and working? 8. Frequency of oscillations of ring oscillator? 9. Reset synchronizer circuit and working with waveform? 10. AHB Protocol working with waveforms? 11. Problem on Multi-cycle path? 12. Different ways of Synthesis optimization? 13. Identify the components that are consuming power in circuit? 14. How to save power in such power consuming block? 15. Dynamic power consumption formula? 16. Low power RTL coding styles?
avatar

ASIC Lead Specialist

Interviewed at Qualcomm

3.8★
Sep 29, 2015

1. How you will verify a block or any module that you designed? 2. Design divide by 3 counters with waveform? 3. Round robin arbitration logic? 4. Sequence detector (overlapping and nonoverlapping)? 5. Verilog code for synchronous and asynchronous flip-flop? 6. CMOS inverter circuit diagram and characteristics? 7. Ring inverter circuit and working? 8. Frequency of oscillations of ring oscillator? 9. Reset synchronizer circuit and working with waveform? 10. AHB Protocol working with waveforms? 11. Problem on Multi-cycle path? 12. Different ways of Synthesis optimization? 13. Identify the components that are consuming power in circuit? 14. How to save power in such power consuming block? 15. Dynamic power consumption formula? 16. Low power RTL coding styles?

Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.
avatar

ASIC Verification Engineer

Interviewed at Qualcomm

3.8★
Jul 17, 2011

Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.

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