Two questions： 1. 2 2bits comparators to 4 bits comparators, and reduce the delay to 1 units 1. data buffer like 0100000001, most simple rtl design to get the length (which is 9)
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
design sensor with minimal logic block
Write a Fibonacci number generator in Verilog, output a number in each cycle.
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
Digital Design basics
explain about cache
What is a fpga and what is a lookup table?
ok. fifo..design n implementation.and other designing questions
The interview was straight forward and aveage
where do you see yourself in 5 years
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