What is setup/hold time?
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
How to reverse a singly linked list?
Flash adc can be used for 15 bit.
Logic question to verify the design How would you verify 3 blocks with incorrect label ? suppose one with apple 2 with orange 3 with apple & orange.
White-board diagram of a block with one input pin (+ clock), and one output pin. The input is a serial stream of data. The output =1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog. Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.
Describe several methods for low power design
Use min 2 input NAND to build a 3 input NAND
Will the CMOS NAND gate speed up by increasing VDD?
tell me about uvm testbench top
What Is UVM? What Is the Advantage Of UVM?
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