How would you make Clock dividers?
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
question-based on aptitude then 1 question on Flip flops
Personality is the most important thing.
which metal layer used for power/clock
How to make an AND gate with only XOR gates
How to process a high rate signal in low frequency clock.
varies and based on JD
I felt the most difficult question was about different metal layers and their properties
Draw: Make a NOT gate using only NAND gate(s).
Write some verilog for a 3 to 1 arbiter, with a priority client and 2 clients in a round robin.
Viewing 301 - 310 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerSenior Vlsi Design EngineerVlsi EngineerAsic Physical Design EngineerSenior Asic Design EngineerSoc Design EngineerRtl Design EngineerHardware Asic Design EngineerPhysical Design EngineerSenior Dft-ingenieurHardware Engineering ManagerHardware Asic Ontwerp IngenieurSenior Fpga Design EngineerFpga Design EngineerFpga Development EngineerSenior Hardware Design EngineerSenior Asic Fpga Design EngineerAsic Design Verification Engineer