They asked questions about Object Oriented Programming : inheritance, abstraction, polymorphism. Other topics : pointers
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
Tell me how your previous co workers would describe you.
1. What is setup, hold time. Reason of metastability. 2. How to reduce setup time, hold time. 3. A C code to check if a given number is divisible by 2 4. Difference between mealy and moore machine 5. Project and resume based questions
Questions based on CV mostly questions are from SV, UVM, Protocols
question related to the digital design asnd c and aptitude are asked
Verilog code for D-flip flop
Tell me about your self
Basic verilog questions, simple logics, and few opps concepts
UVM Analysis ports and uvm testbench
tell me the UVM testbench execution flow
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