write a verilog code for a latch
Design Verification Engineer Interview Questions
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1. what is the alternate for analyis port 2. related to fork join 3. interrupt handling
Tips for round 2- keep your basics strong. Don't need much. Just got get played by interviewers. If you're stuck or don't know the answer. Atleast try for an approach and keep asking for feedback. Before solving any question, explain your approach and then proceed. Your behaviour shouldn't be like digital systems, either 0 or 1. It should be like analog. Keep explaining every step. And don't say anything that you can't explain. Tips for round 3- Just don't lie. Speak the truth. Don't mention GATE scores in CV. Deny any further studies plan from your side. Just say that you'll do it if your firm wants you to upgrade your skills and be more productive for firm. Else you have no plans. Preferred location - Always say Noida.
They asked me about uvm
Where do you see yourself in 5 years?
apptiude was about the quantative, digital and a simple program. digital question are also simple you can search on internet. programming are also questions.
Explain all the steps of ASIC flow in detail
Debugging scenarios of latest project
What relevant experience do you have in this role? Are you familiar with HIPAA compliance?
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