Q: What is the use of the factory in UVM?
Design Verification Interview Questions
3,713 design verification interview questions shared by candidates
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Virtual Methods , Virtual classes and their difference in system verilog
Questions around GPU pipeline and how it works. Command streamer etc
Draw the IDD diagram (current as a function of time) of an inverter when the input switches from OFF to ON.
Shuffle a array Given an array, write a program to generate a random permutation of array elements. This question is also asked as “shuffle a deck of cards” or “randomize a given array”. Here shuffle means that every permutation of array element should equally likely.
technical interview first, then HR interview
how do you verify 32 bit adder
Basic C Verilog Computer Architecture
Name and describe the differences between SystemVerilog forks.
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