Static timing analysis (writing max, min delay, multi cycle path, false path), clock domain crossing (for 1-bit, multi bit), Coding questions, questions on previous projects
Soc Engineer Interview Questions
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BASIC questions on cyber security
design traffic light what main things to consider. sr latch. leadership questions
1. Static and dynamic power 2. How to fix setup and hold time violation without adjusting clk frequency? 3. Significance of VT 4. Subjects of 1st and 2nd semester in mtech. 5. RTL to GDSII 6. Basics of design for testability.
Explain stuffs in my resume
define a function in python language
Pipeline stages in common computer architecture. Why does it has to be 5 stages? Critical path solving question with 5 cascading xor gates.
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
How transistor works and design logic circuit base on a problem given ?
Asynchronous FIFO, Setup/Hold time, CDC, reset
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