Knowledge of IR, OffSec, port ranges, log analysis, Network protocols.
Soc Interview Questions
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how to investigate a phishing email.
Initiative
How does clock skew affect the operational frequency of this circuit.
need technical question
SystemVerilog Basic, Didn't touch upon UVM. OOPS Concepts, Virtual keyword etc.,
Resume Based Questions SoC design flow State Machine code
1. Static and dynamic power 2. How to fix setup and hold time violation without adjusting clk frequency? 3. Significance of VT 4. Subjects of 1st and 2nd semester in mtech. 5. RTL to GDSII 6. Basics of design for testability.
STATIC TIMING ANALYSIS
Pipeline stages in common computer architecture. Why does it has to be 5 stages? Critical path solving question with 5 cascading xor gates.
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