Our Senior Component Validation Enginee r:
- Defines, designs, and develops complex radio frequency integrated circuits in IPs and SoCs and creates verification test plans for RF validation.
- Conducts transistor level feasibility analysis, defines floorplan and layout for RF circuit architecture, creates test benches, and verifies and debugs design to meet the desired specifications.
- Reviews system specifications and design plans to ensure that designs meet customer needs and is compliant with applicable codes, standards, and regulations.
- Designs new product concepts and prototypes, creates detailed drawings of circuit designs, and develops and analyzes test procedures.
- Performs radio signal path and ensures detailed transistorlevel design for transceivers, RFIC blocks, wireless applications (4G, 5G, WLAN, Bluetooth, and GPS).
- Applies understanding of electromagnetic theory, communication theory, radio frequency test equipment, RF and wireless circuit design, RF system analysis, RF system block characterization, and specification to resolve issues and conduct RF verification.
- Master degree in relevant field with a minimum of 7 years of experience in validation of analog/mixed-signal/RF building blocks (ADC/DAC/PLL).
- Development of measurement automation software and platform firmware for analog/RF IP characterization.
Nice to have :
- RF background with hands on experience in 5G/6G cellular system measurements is a plus.
- Excellent oral and written communication skills and ability to contribute and work in a multi-site team setting is also a plus.
This position is subject to the collective agreement for workers and employees in the electrical and electronics industry, employment group H: https://www.feei.at/wp-content/uploads/2025/09/caeei-2025-08-25.pdf
A higher payment is negotiable depending on your expertise and skills.
Prior to entering an employment agreement, the employee will be asked to provide all documents and references to verify any service times of prior employment. Based on provided documents the appropriate number of service years will be credited as prior employment.
Experienced Hire
Shift 1 (Austria)
Austria, Villach
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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We offer a total compensation package that ranks among the best in the industry.
Annual Salary Range for this job which could be performed in Austria is: €66,680.00 - €117,253.00

The compensation range displayed in this posting reflects the minimum and maximum target compensation for this position. Within this range, individual pay is determined by job related skills, experience, and relevant education, training. As part of our total compensation approach, the final offer may include additional pay components and benefits. Your recruiting team will share the confirmed base salary along with any applicable total compensation elements upon employment offer delivery.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
