I applied online. The process took 5 days. I interviewed at AMD (San Francisco, CA) in Apr 2023
Interview
First round was an aptitude and some technical questions. It was for a senior position. Interviewed by Manager. This was for a senior role. The interview was for one hour.
Interview questions [1]
Question 1
A router transmits the data. If the data is destined for same address then the packets should arrive in the same order as it is transmitted. The packet sent second is not allowed to overtake the one sent first. But if the packets are destined for different address it can overtake the other packet. How will you verify this design. The packet does not contain any ID.
campus interview . 2 rounds, basic questions from STA , cmos, digital basics , verilog questions, verilog code for asynchronus d flipflop, blocking and non blocking statements, structure of 3 input OR gate, explain about static and dynamic power
1. HR Screen
2. Technical Round
The whole process was around 2 weeks.
You first get a call from the HR and then will answer questions.
If you are successful, you will book a time for a technical interview.
Interview questions [1]
Question 1
Tell me the difference between combinational and sequential logic
I was not well prepared, It was basic q and a related to my current role and some basic OSI questions, Also interviewer was great he gave me time to understand the question and helped me with the hints
Interview questions [1]
Question 1
A chip was given which performs (001)addition,(010) subtraction, (011)multiplication and division(100) on 8 bit value, it can store 20 operands at a time in a stack and 2 bits for error handling,
Arth overflow
Stack over
1.Questions was to find out end cases and possible errors and how can we handle it in verilog test benches?.
2. Also, How to write those test cases. ?
