I applied online. The process took 3 weeks. I interviewed at AMD (Austin, TX)
Interview
- Very specific and interactive where the interviewer engages in the problems.
- They look for your understanding of the problem and your approach of solving it no specific syntax or method is required
- It was two rounds, first over the phone second on site. I had a third round interview specifically to test my SystemVerilog OOP knowledge which was specified before the interview.
I applied through an employee referral. The process took 1 day. I interviewed at AMD (Bengaluru) in Oct 2017
Interview
First round was a 1 hour screening test, comprising of 6 sections, out of which any 4 could be chosen. However, the Digital Design and Logical Reasoning sections were compulsory.
The screening was followed with an interview. They mostly asked me data structures and algorithms questions with the focus revolving around caches.
Interview questions [1]
Question 1
You are given the following linked list: A->B->C->D->E->NULL. The head points to C currently, and C needs to be deleted while keeping the structure of the linked list intact. Note: This is a singly linked list.
I applied online. The process took 1 day. I interviewed at AMD (Bengaluru) in Nov 2016
Interview
It was total 6 rounds of Interview, starting with SystemVerilog, UVM, projects, analytical,SOC level. did not find it much difficult.
analytical questions were tricky, but enough time was given to answer each.
Interview questions [1]
Question 1
UVM question : Assuming, UVM environment has 3 different agents having scope to their own interfaces.
On driving wrong stimuli on agent1, there will be error pin asserted on interface3(monitor of agent2 sees this).
soon after error-pin assertion, there should be a read transaction from agent2.
How do you make sure your agent2 drives a read transaction on every wrong stimulus from agent1, which was seen on a monitor of agent2 ?