I applied online. The process took 12 months. I interviewed at Intel Corporation (Washington, DC) in May 2024
Interview
Experienced professional as SoC Design Engineer with expertise in GPU architecture, SoC globals including Clocking, reset, low power design and chassis components. STA, system verilog, SoC clock architect for Intel's Alchemist and Battlemage GPU.
Micro architect for SoC globals including clocking, reset, low power, registers and debug networks.
Interview questions [1]
Question 1
1. what are inertial delay and transport delay?
2. Circuit using D latch, master slave FF & explain it
3. how u will reduce the input frequency? draw the circuit & explain
4. D FF Verilog code
I applied through an employee referral. The process took 3 weeks. I interviewed at Intel Corporation (Heredia) in Jul 2022
Interview
Entrevista con los manager, realizaron preguntas sobre, circuitos digitales, arquitectura de computadoras, verilog y Python. Especificamente sobre cosas básicas, como mapas de Karnaugh, reducciones booleanas, comandos basicos de Python y partes de un procesador.
I applied online. The process took 4 weeks. I interviewed at Intel Corporation (Kulim) in Mar 2024
Interview
The interview started with looking into my CV, and point out that VLSI modules are related to their field. They asked me to talk about my VLSI design project that is written on my CV. Then, some technical question about programming and digital system. In the end, they talked about what would I do if I were to get offered
Interview questions [1]
Question 1
Program to differentiate even and odd number
Draw and explain NOT and NAND gate
Draw a stick diagram for NOT gate
Find ways to make NAND gate a NOT gate
Explain methods of verifying your design, such as DFT Scan path.