Glassdoor users rated their interview experience at NVIDIA as 100% positive with a difficulty rating score of 3 out of 5 (where 5 is the highest level of difficulty). Candidates interviewing for Sr. Machine Learning Engineer and rated their interviews as the hardest, whereas interviews for Sr. Machine Learning Engineer and roles were rated as the easiest.
The hiring process at NVIDIA takes an average of 21 days when considering 1 user submitted interviews across all job titles. Candidates applying for Sr. Machine Learning Engineer had the quickest hiring process (on average 21 days), whereas Sr. Machine Learning Engineer roles had the slowest hiring process (on average 21 days).
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I applied online. I interviewed at NVIDIA (New York, NY) in Feb 2024
Interview
Only did the OA, did'nt get any interview follow ups after. In the OA it was around 10 questions within an hour. The first three were Leetcode easy+med, afterwards I got some ML knowledge and sql questions.
Interview questions [1]
Question 1
I got asked leetcode questions plus hacker rank sql practice questions. Alongside some questions about sql works.
I applied through an employee referral. I interviewed at NVIDIA (Santa Clara, CA) in Aug 2025
Interview
First Screening Round
* 2 basic RTL Questions, 1 Scripting
* Blocking vs non blocking, reg vs wire
* Python scripting question: file I/O, basic string parsing
* 2nd RTL question: Basic 2 stage adder, design Verilog module given circuit description
* Some resume questions
Second Screening Round
* Advanced scripting question on retiming registers
* RTL question on accumulating data per address
* Some theoretical FIFO questions (no code)
* Packed vs unpacked arrays in depth
Panel Round
First Round
* Basic scripting question on data conversion and string parsing (CSV)
* Open-ended question on finding an error in a mux-based programmable delay circuit
* Resume questions
Second Round
* Designing a 10:1 mux using 3 4:1 muxes
* 80:20 to 8:2 module, FIFO depth
Third Round (Hiring Manager)
* Fibonacci Sequence in Python: Iterative and Recursive
* Fibonacci Sequence in Verilog: Serial approach, FSM Design
* Detailed discussion about team functions, responsibilities, day-to-day job
Fourth Round
* 4x4 multiplier in Verilog
* Optimize to pipeline multiplies
* Optimize to use a single MAC unit and serially feed in data
* Second largest sum in a Python list
Fifth Round
* Debugging a Perl script
* A lot of questions about intermediate expressions in Verilog and data-loss
Interview questions [1]
Question 1
First Screening Round
* 2 basic RTL Questions, 1 Scripting
* Blocking vs non blocking, reg vs wire
* Python scripting question: file I/O, basic string parsing
* 2nd RTL question: Basic 2 stage adder, design Verilog module given circuit description
* Some resume questions
Second Screening Round
* Advanced scripting question on retiming registers
* RTL question on accumulating data per address
* Some theoretical FIFO questions (no code)
* Packed vs unpacked arrays in depth
Panel Round
First Round
* Basic scripting question on data conversion and string parsing (CSV)
* Open-ended question on finding an error in a mux-based programmable delay circuit
* Resume questions
Second Round
* Designing a 10:1 mux using 3 4:1 muxes
* 80:20 to 8:2 module, FIFO depth
Third Round (Hiring Manager)
* Fibonacci Sequence in Python: Iterative and Recursive
* Fibonacci Sequence in Verilog: Serial approach, FSM Design
* Detailed discussion about team functions, responsibilities, day-to-day job
Fourth Round
* 4x4 multiplier in Verilog
* Optimize to pipeline multiplies
* Optimize to use a single MAC unit and serially feed in data
* Second largest sum in a Python list
Fifth Round
* Debugging a Perl script
* A lot of questions about intermediate expressions in Verilog and data-loss
Phone screening interview with HR first then the online technical interview with hiring manager for resume screen. It toook about 30 min. I got an email of interview result after 2 weeks.
Interview questions [1]
Question 1
He requested to compare with LPDDR and HBM and how to control impedance control.