What was the thesis topic and try to explain it?
Analog Design Engineer Interview Questions
1,257 analog design engineer interview questions shared by candidates
Find Kmap minimization and draw gate level circuit
1. A question on low-pass filter for current input and output. 2. A question on the loop stability of a PLL. What could be done to improve the stability? 3. A question on a passive switched-cap circuit with multiple clock phases. 4. A question on R-ladder and which node has the largest noise voltage (rms) 5. Multiple RC circuit questions with pulse and step inputs on different R and C combos and different structures. 6. A question on VCO phase noise; a question on the effect of duty cycle variation on phase noise. 7. A question on VCO swings (Q-factor/ bias current etc).
RC , CS amplifier, differential amplifier, CMOS inverter , MoS capacitor
Following questions about your phd presentation.
Detailed discussions on PLL, Op-Amps, common transistor amplifiers, Differential amplifiers.
advanced analog IC design related questions
Bode Plot, Project related questions, Resume related questions, Bandgap reference, Noise analysis, OTA circuit analysis, ICMR, Output ranges, Current mirrors, Basic MOSFET fundamentals, Data converters, and Switching circuits.
what is set up and hold time?
RLC CIRCUIT ,charging and discharging and their wave form
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