Everything about metastability, fsm. FIFO buffer in CDC. Setup time, hold time equations. Questions on counters and how to make synchronous and asynchronous counters using JKFF. On site is 8 rounds 45 min each. It was tiring but everyone is welcoming and very knowledgeable. Beware of an Indian Guy. He was very rude.He asked me to present code for my verilog projects instead of questions. He asked me several questions one after another with a time lag of like 4 seconds and would not let me answer them. He then left making disappointing comments. It was my last round of interview everyone apart from him were great.
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
Which project should I question you about?
Basics of CMOS at transistor level.
What is Scan, memBIST, and logicBIST? usually what percentage of test coverage of suck-at requested? what % of at-speed transition test?
How do credits work in protocols
Code a synchronous fifo in verilog
Basic questions on Verilog Combinational and sequential coding differences, Coding a state machine, Timing problems Was asked to explain my projects
rate yourself in c and vlsi
How to realize a communication between different time domain?
what are sorts and tell different types of sorts ?
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