the questions that were asked were basic digital design was asked to design a mod 10 counter using t flip flop
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
Describe one of the problems related to Dynamic logic and the solution to it
About my understanding of layout tools, the environment and fluency on the design flow.
verilog - basic programs on counters ,blocking non blocking,intra delay and inter delay etc... how to calculate maximum frequency when two flipflops in between combinational paths are given. next focus on academic project,networking protocals.
Please specify three ways to solve setup and hold time violation and how would you implement your solutions in verilog?
Tell me about yourself and work experience? Explain ASIC flow? What is Scan chain insertion? USe? What is scan chain reordering? Why macros are placed preferably at boundary and not at centre? What all physical only cells you cam across ? Explain? Checks before placement? How do you fix timing at Place? Difference between CCD and CTS? What is HFNS? Why it is not done at syn? Aim of CTS? What happens in route? What are NDR ? Explain side flows? Types of placement blockages? What is derate? what is LVS? what is FEV? Kind of buffers used for CTS? How do you select them?
What are the ways to synchronize signals and busses?
Present the previous projects
Questions about clock domain crossing issues. How to avoid them.
How to verify a design? What do you know about your verification env? Do I know any AMBA protocol? Do I use shell script? or any other script language?
Viewing 111 - 120 interview questions