You are given 2 receiver antennae and one transmitter antenna. Describe what happens to the received signal when changing the distance between receivers (close and far apart).
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
Write the verilog of ROB on a paper.
Standard digital design questions: 1. FSM 2. Multiplier design/questions 3. sync vs async reset
Cache coherency, mapping techniques, metastability, cdc, synchronizers,
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
write assertions to verify the condition.
Linked list, Bit manipulation, Pipeline
basic concept of pipeline state machine of sequence detector C program of a function about pattern replace
STA algorithms.
Phone interview Design gates using CMOS transistors. Build gates using 2-to-1 muxes. Write a verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency. The number of states required for a sequence recognizer.
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