Moderate, no unexpected questions asked.
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
What will gm change if we enlarge the W/L of a transistor by 2. Compare the gm of a BJT and MOS device. Slew rate problem
write a verilog code of moving average
min and max timing violation
You are given 2 receiver antennae and one transmitter antenna. Describe what happens to the received signal when changing the distance between receivers (close and far apart).
Write the verilog of ROB on a paper.
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
What is multicycle path, what is CDC?
They concentrate more on your technical knowledge over Architectural Design and Problems you tackle. As well as a Ciding for Automation
One hot encoding, FSM divide by 3, Verilog coding.
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