Design a FSM of Moore Machine to detect 0110 sequence.
Asic Design Engineer Interview Questions
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DV team lead asked a question about mathematical proof for paired prime numbers characteristic.
1. Difference between SystemVerilog and Verilog. 2. Difference between nonblocking and blocking. 3. Difference between asynchronous and synchronous. 4. How can you observe and solve the problem if there is a timing violation (related to setup time and hold time)
what is clock uncertainty what is skew
What is the CMOS
Verilog description of logic. Digital logic questions
Types of coverage?
Is it better to compare to an immediate or zero?
I was asked to create XOR gate using only NOR gates.
State machine for detecting the sequence 101011
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