> Asked questions related to fifo. Was not a direct question , they have explained a particular scenario with combination of fifos along with pictures , and the question will be crystal clear. > Multiple questions were there based on basic test bench architecture and how to build a test bench with a given design as example
if the inverter's input is connect to its output. how the output voltage curve should be like
In technical interview, they asked: (1) about yourself (2) where did you hear the company (3) explain fundamentals regarding electronic elements e.g. diode, bjt, fet, opamp, capacitors (4) college thesis (5) what should they expect from you
What should be the size if it is receiving data and also loosing some packets ?
Round 1 1- Two to Three Q's on Projects done 2- Designing Q - Consider inputs coming at every clock. I want the output at time = t to give me sum of all nos coming before that time. (Adder is normal adder with latency 1) 3- Designing Q - Consider the same output needed, but adder has a latency of 2. So input is taken at every clock and output is given at every clock. But Input at t=0 is received at output at t=2, input at t=1 is received at output at t=3...
Which is better, setup time or hold time violation?
choose right cache strategy
QUestions were very simple like given a program whats is the output, phases in UVM, implementimg gates using muxes etc.
1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
Design OR gate using MUX
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