How to check if a fabricated chip has a hold time violation, and how to fix it.
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
1st is HR, ask about why Nvidia? expected salary, immigration status, graduation date, etc. 2nd ask about verification methodology (UVM, OVM), system verilog (passing obj as function argument, different type of fork-join, polymorphism etc), use and function of interface in testbench. 3rd ask about arbiter design, setup/hold time, basic logic design, 4rd ask about programming (how to find loops in a linked list), basic C programming and divide by 3 divider. 5th is hiring manager, talk about positions, teams and their products. ask about basic logic design, verilog(syn, asyn, blocking, non-blocking), transistor level design of registers and what could be problem with that design. 6th dude is a funny guy who ask about nothing but just keep talking about the team, what he has done and what he like and don't like about his job, etc. Most difficult: design divide by 3 divider with 50% duty cycle, I don't know how to do that, and the recruiter change the duty cycle to 66%, and I finished it.
calculate the addressing of a 4-way set associative cache for a given size
The second questions is about Combination logic, to conter the first 1 bit in the 8192 data stream. the output it in 13-bit index. it is a little difficult!
there is a disk half painted white and the other half black. There are two sensors and the outputs of these sensors are the only signals available. How will you determine if the disk is rotating clockwise or anti-clockwise?
nor gate with one input 0 and one input C what is its output status
FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.
Write a verilog code to swap data with and without a temp register.
explain what is the best time (morning, afternoon or night) and place (beach, valley etc) could a hot-air balloon fly highest? How is the structure of a concert theater ?
There are 8 bits inputs ,only use full adder to detect how many logic 1's
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