mostly regular
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
Describe the 5 stages in MIPS pipeline structure.
verilog basic, C++,C basics
fifo design
how abot time borrowing in Latch,Tell us about clock control and why it can be done
The phone screen with basic questions like your visa status.
Bus protocols like SPI, ARM etc
Draw the contents of an asynchronous FIFO.
How to turn a 40% duty cycle clock signal to a half frequency signal with 50% duty cycle.
how would you code an adder in verilog
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