Asic Design Engineer Interview Questions

1,316 asic design engineer interview questions shared by candidates

Questions 1st technical interview: Talk about yourself Talk about your project networks problem from question paper how does the power supply at home work between two to three rooms Flip flops timings questions frequency of 11 inverters in series detailed questioning of NMOS structure operations functioning secondary effects probe into channel length modulation CMOS inverter switching power there, static power and dynamic power formula logical puzzle:consider 2 taps (tap a and tap b) as inputs AND gate OR gate and XOR gate then take the same logic and build a water tank, locate the taps so that the functionality of the gates hold good Questions I got wrong in the question paper Resume-based questions
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ASIC Design Engineer

Interviewed at OpenFive

3.8
Apr 5, 2015

Questions 1st technical interview: Talk about yourself Talk about your project networks problem from question paper how does the power supply at home work between two to three rooms Flip flops timings questions frequency of 11 inverters in series detailed questioning of NMOS structure operations functioning secondary effects probe into channel length modulation CMOS inverter switching power there, static power and dynamic power formula logical puzzle:consider 2 taps (tap a and tap b) as inputs AND gate OR gate and XOR gate then take the same logic and build a water tank, locate the taps so that the functionality of the gates hold good Questions I got wrong in the question paper Resume-based questions

1st technical interview: Talk about yourself Talk about your project networks problem from question paper how does the power supply at home work between two to three rooms Flip flops timings questions frequency of 11 inverters in series detailed questioning of NMOS structure operations functioning secondary effects probe into channel length modulation CMOS inverter switching power there, static power and dynamic power formula logical puzzle:consider 2 taps (tap a and tap b) as inputs AND gate OR gate and XOR gate then take the same logic and build a water tank, locate the taps so that the functionality of the gates hold good Questions I got wrong in the question paper Resume-based questions 2nd technical interview: Out of the box thinking helps here project related question: gaussian distribution a lot of static timing analysis questions, tricky a D FF with clock input as an AND gate with inputs A and clk, now remove AND gate to give a clean clk but the functionality of the circuit should remain the same. talk about the kind of job they do, the kind of job I want to do, offers at hand, training details, date of joining details HR round: A talk about future aims of my life and culture at OS, the perks of being a small company, etc etc
avatar

ASIC Design Engineer

Interviewed at OpenFive

3.8
Sep 23, 2013

1st technical interview: Talk about yourself Talk about your project networks problem from question paper how does the power supply at home work between two to three rooms Flip flops timings questions frequency of 11 inverters in series detailed questioning of NMOS structure operations functioning secondary effects probe into channel length modulation CMOS inverter switching power there, static power and dynamic power formula logical puzzle:consider 2 taps (tap a and tap b) as inputs AND gate OR gate and XOR gate then take the same logic and build a water tank, locate the taps so that the functionality of the gates hold good Questions I got wrong in the question paper Resume-based questions 2nd technical interview: Out of the box thinking helps here project related question: gaussian distribution a lot of static timing analysis questions, tricky a D FF with clock input as an AND gate with inputs A and clk, now remove AND gate to give a clean clk but the functionality of the circuit should remain the same. talk about the kind of job they do, the kind of job I want to do, offers at hand, training details, date of joining details HR round: A talk about future aims of my life and culture at OS, the perks of being a small company, etc etc

1. Build a circuit to ti produce a signal high whenever output changes also asked this to be implemented in terms of FSM suitable for RTL CODING. Asked about data dependencies and control dependencies, caches types and cache replacement policies. What is virtual fiction in c++ and recursive functions code in c Mostly basics
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ASIC Verification Engineer

Interviewed at Ambarella

4.4
Oct 19, 2019

1. Build a circuit to ti produce a signal high whenever output changes also asked this to be implemented in terms of FSM suitable for RTL CODING. Asked about data dependencies and control dependencies, caches types and cache replacement policies. What is virtual fiction in c++ and recursive functions code in c Mostly basics

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