cross clock domain questions
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
asynchronous clock domain crossing, FIFO pointer logic, timing constraints, a divide by 3 clock generator
How to build a fsm sequence detector
Where do you see yourself in 5-10 years?
Some cutting square questions,
Problem on timing analysis
What is aliasing, and how can you make sure you aren't reading an aliased signal of unknown frequency on an oscope?
Decimal to gray function with logic gates
Be strong in your basics
Why do we use gray code in sampling than binary? Depth of Fifo. writer is writing 6 locs in 10 units and reader is reading 60 locs in 100 units. But both of them once they start they keep reading /writing. Depth of buffer ? (Ans. 24) It took some for me to understand. His accent was weird. Puzzle: There are 30 people in party. What is the probability that no two of them have birthday on same date ? (you will find this on careercup)
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