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Asic Layout Design Engineer Interview Questions
23 asic layout design engineer interview questions shared by candidates
About my understanding of layout tools, the environment and fluency on the design flow.
what is an FSM
Explain setup and hold time.
Explain CDC and how can it be addressed?
Describe the process for design of a new architecture and the refinement process
DV team lead asked a question about mathematical proof for paired prime numbers characteristic.
1. Difference between SystemVerilog and Verilog. 2. Difference between nonblocking and blocking. 3. Difference between asynchronous and synchronous. 4. How can you observe and solve the problem if there is a timing violation (related to setup time and hold time)
In technical interview, they asked: (1) about yourself (2) where did you hear the company (3) explain fundamentals regarding electronic elements e.g. diode, bjt, fet, opamp, capacitors (4) college thesis (5) what should they expect from you
Draw a inverter in logic form and in CMOS configuration. And explain the physics behind it.
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