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Associate Engineer Interview Questions
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TECHNICAL INTERVIEWS: Out of 99 students appearing for the OT, 33 odd students were called for the Technical Interview Round (Selection Ratio >= 30%). The students appearing for the Technical Interviews were again segregated into three categories, basis their Area of Specialisation. Generally, the Interview Process comprises of two Technical Discussion Rounds which may extend to three followed by an HR Round if you get through convincingly. Unlike Regular Interviews, QC Interviews are intriguingly technical, and don’t start off with “Introduce Yourself” questions. The Interview started with listing down my subjects of comfort. As my profile mostly comprised of projects and internships aligned to VLSI Design, the conversations mostly emphasised on testing my basic concepts of CMOS Circuits. The important questions I faced in my first round were as follows: ROUND 1 DESCRIPTION: Q1: Design NAND Gate using 2:1 MUX. Draw a 2 i/p AND Gate using XOR gates. Q2: Draw a Binary to Gray Code Converter. Explain the steps followed. What are the advantages with Excess 3 Coding? Q3: Questions on Flip-Flop Conversion. Explain the difference between Moore and Mealy State Models. Q4: Explain the Concept of Small Signal Analysis. How are MOSFETS used as Inverters and Amplifiers? Q5: Explain CLM in MOSFETs. Write down the relation between Threshold Voltage & Source to Body Bias. Q6: Explain DIBL, is it good or bad? Q7: What are various power losses in digital ICs and CMOS? Q8: Explain Dynamic Switching Power Losses in context to Digital ICs. Explain other power losses if you know them. How do you minimise Dynamic Switching Power Loss? After an hour-long discussion on the above topics, I was taken into Communication Engineering, Software Applications & Embedded Systems. Questions were mostly from Digital Signal Processing, Analog & Digital Communication Systems in my second round. ROUND 2 DESCRIPTION: Q1: What is Bit Interleaving? Explain the conventional techniques used for Bit Interleaving. Q2: Draw the Constellation Diagram for QPSK Modulation. Is this diagram the most optimised one? (Relate to Probability of Error) Q3: What is the Multiplication Property of Fourier Transform? Draw the Fourier Transform of Rect, Sinc and Triangle Waveforms. Q4: Write down the Properties of Dirac Delta Function Q5: What are the Characteristics of Super-Heterodyne Receiver? Q6: Draw and explain the Block Diagram for QAM System. Define Signal. What are the conditions for Stability & Causality of Signals? Q7: Derive the Shannon’s Channel Capacity Theorem. Is it possible to achieve infinite data rate? Q8: What are the differences between Sampling & Quantization? Why is Sampling followed by Quantization and not the other way round? Q9: Compare FIR and IIR Filters. What is a Linear Phase FIR Filter? Q10: What are the various search algorithms you are aware of? Explain the Binary Search Algorithm. ROUND 3 DESCRIPTION: The Technical Discussion Rounds were followed by an HR Discussion. We discussed more on the Job Profile being offered. It was a very satisfying process for me, with 12 selections from BIT Mesra (Selection Ratio >= 30%).
About Vlsi circuits and digital.
Based on your resume, tell me about the kind of company would you work for?
INSERT AND REMOVE Operation from Binary Tree. OOPS Concepts
about filters
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