Decribe the structure of speakers.
Circuit Designer Interview Questions
232 circuit designer interview questions shared by candidates
why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc
Why there is a pinch-off during saturation mode of a CMOS device?
Whether you have any silicon layout experience?. What happens if the capacitor is connected between the output and input nodes of the common source amplifier.
Recruiter questions: 1. Why this job? 2. What happens to performance of invertor when body is tied to -ve voltage? 3. How will propagation delay of invertor scaled with sizes of PMOS and NMOS? Director phone screen: 1. MOSFET capacitance variation with gate voltage, list three regions this C. 2. I-V characteristic of NMOS whose drain is tied to Vdd, Source/Body to Gnd and Gate.voltage is sweep from 0 to Vdd. Mention different regions of this curve. 3. How will NMOS drain current scale with temperature variation? 4.Consider a blackbox circuit that sources current 'I'. What tests will you perform on it?
How do you size NFET/PFET of inverter to change switching voltage.
What is the difference between latches and flip-flops? What is the output of a flip-flop if the output is passed through an inverter and then fed back to the input?
High-pass and low-pass RC filter, AND/OR gate with 2:1 Mux
Mobility questions, how to build a NAND and NOR gate, and the one I failed was about a transistor in cutoff where you need the drain voltage.
"Tell us your greatest strength and weakness?", "Where do you see yourself in five years?", "Why should we hire you?", "How is your support system?",
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