current mirror, single stage amplifier, OP-amp, ADC
Design De Ic Interview Questions
584 design de ic interview questions shared by candidates
What is the difference between := and :/ in SystemVerilog?
Power dissipation. Clk design. Logic desig
In the final round , I was asked some logic puzzle which was unexpected, I took some time but finally solved it.
nothing was difficult
There was no such difficult trick in every question. Just not to try to answer if you do not know the exact answer.
Technical questions on cross clock domain synchronization, metaflops, slightly complex verilog questions, setup and hold time, basic questions on C++.
one of the interviewers got really detailed about system verilog constrained randomization process
Thought it would be mostly circuit related questions but instead it was heavy on DSP. Questions are basic, was able to answer most of them.
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