Why do we need a virtual interface?
Design Verification Engineer Interview Questions
3,719 design verification engineer interview questions shared by candidates
Asked about Basic Signalling like Block Section Working, Logic Circuits, Control Table Checking, Signalling Plan, CBTC Principles, Automation in C#, Process Automation & outcome. Success Ratio & feasibility of Automation in Signalling
technical questions which are related to projects you have done
c++ basics - virtual functions, function vs task difference, coverage , constraints
write assertions for the given timing diagram
Tell me about yourself and your skills
SV, UVM, Driver sequencer handshake mechanism
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
Verilog code for basic circuits
Basic Questions; What are your greatest strengths?
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