Why would you want to work this company?
Design Verification Engineer Interview Questions
3,718 design verification engineer interview questions shared by candidates
* job experience and roles * how do u verify a scheduler * A block has inputs of network pkts and buffers/pipelines them through an RTL. RTL has counters which will tell how many packets are sent. How to verify? (Counters Read => count. Write => clear) How to verify counts? what cases will u test? * Given a sys verilog code for a memory model and asked to implement read/write/move functions and write checks
MEmory related coding and DRAM related questions
static timing analysis
network theory
In UVM, what if we register a component in object utils.
What are the three important things of being a leader.
leetcode was parantesys question Hardware was about memory
Systemverilog and UVM questions
Why do you think you would be a good fit for this position?
Viewing 2861 - 2870 interview questions