Why Qualcomm?
Design Verification Engineer Interview Questions
3,716 design verification engineer interview questions shared by candidates
question around the system verilog ,verification methodology.
System Verilog Virtual functions
System Verilog ,UVM Basics, Questions on Resume. Assertions,Constraints. Memory Verification plan
Constraint for 8-bit opcode (SystemVerilog) ➤ Only one bit can be set in the 8-bit opcode (i.e., one-hot encoding). Matrix size based on opcode bit index ➤ Based on which bit is set in the 8-bit opcode, generate a square 2D array (e.g., if bit 4 is set, matrix is 4x4).
Constraint randomization based question linking to AXI and memory filling
Confidential. But related to system verilog and uvm.
how to impliment A=7.5B w/o using *, /
How could you shorten the period of training?
Since the interview was for a hardware position, they asked more software related questions than I expected but were all easy
Viewing 2911 - 2920 interview questions