bitmasking using systemverilog C++ classes
Design Verification Engineer Interview Questions
3,716 design verification engineer interview questions shared by candidates
Four people need to cross a rickety bridge at night. Unfortunately, they have one torch and the bridge is to dangerous to cross without a torch. The bridge can support only two people at a time. All the people don’t take the same time to cross the bridge. Time for each person: 1 min, 2 mins, 7 mins, and 10 mins. What is the shortest time needed for all four of them to cross the bridge?
3. A linked list that is one-directed, how can you tell there is a loop without using another data set? You can write it in pseudo-code
more on application oriented uvm config_db and resource_db register bits swapping verification fifo based questions
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
What is the terminal command for checking the list of active processes? What is the terminal command for checking the amount of free disk space? What does the '-x' parameter do for the `bash` command? Have you used Docker? Have you used KVM?
Difference between task and function in systemverilog.
What are your goals personally and professionally?
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
working env is to good in the main office.
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