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Design Verification Engineer Interview Questions
3,710 design verification engineer interview questions shared by candidates
1st is HR, ask about why Nvidia? expected salary, immigration status, graduation date, etc. 2nd ask about verification methodology (UVM, OVM), system verilog (passing obj as function argument, different type of fork-join, polymorphism etc), use and function of interface in testbench. 3rd ask about arbiter design, setup/hold time, basic logic design, 4rd ask about programming (how to find loops in a linked list), basic C programming and divide by 3 divider. 5th is hiring manager, talk about positions, teams and their products. ask about basic logic design, verilog(syn, asyn, blocking, non-blocking), transistor level design of registers and what could be problem with that design. 6th dude is a funny guy who ask about nothing but just keep talking about the team, what he has done and what he like and don't like about his job, etc. Most difficult: design divide by 3 divider with 50% duty cycle, I don't know how to do that, and the recruiter change the duty cycle to 66%, and I finished it.
nor gate with one input 0 and one input C what is its output status
What are you currently doing at your present job
FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.
Would you prefer to have setup or hold violations after the chip is manufactured?
You have 25 horses. you can race 5 at a time and get their order from the fastest to the slowest. Find the fastest 3.
There are 5 bowls with 100 candies each. In 4 bowls, all of the candies are 10 grams each. In 1 bowl, all the candies are 9 grams each. Using a digital scale, how can you determine which bowl has the 9 gram candies by using only 1 weighing?
which operator can't you overload in C++
given an array of N integers and int k find out if there are 3 numbers that together sum up to k
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