implementation of driver class based on the figure they gave
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
Discussed about verification projects in resume, how is formal and functional verification different. On coderpad, he gave an RTL code and asked to identify different scenarios and write SV properties of them. The RTL had a buggy FSM and asked me to debug it.
Create xor from mux. And create a state mechine
Explain encapsulation, inheritance, polymorphism. How does a TLB work and why is it necessary?
What would you use a modport for?
Basic system verilog and UVM based questions
How the UVM sequencer and the sequence handshake happens
How do you generate a variable rate clock which is randomized
What is the difference between local, protected and publice. Give an example usage of the three.
Linux: how to create a file, how to find all file that contain FOO, with case sensitive and case insensitive.
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