Regarding Technical skills I don't have any difficulties and regarding job location to change from Bangalore can be difficult
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
Nothing of that sort
not much difficult
Mostly SV and methodology based and also previous projects.
Write the VHDL or Verilog code for a given state machine diagram.
One of them asked about very fundamental elementary questions which was hard to recollect
There was no really difficult question. If I remember clearly, maybe questions on RTL coding style, like always @(posedge clk, reset_active) begin if(reset_active) do somthing else do something end vs: always @(posedge clk, reset_active) begin if(!reset_active) do something else do something end What is the difference in above two impl's.
A basic testplan scenario
At one point, I was asked if I would go to the customer in Texas. It sounded to me like the interviewer was talking about a single trip. I should have asked how much time I would spend in Texas. Later, when the offer came, they wanted me to spend one week out of every month in Texas.
Linux mount filesystem
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