Questions on pipelining
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
register vs flip-flop
What is stuck at fault, transition fault, bridging fault?
1. Programming questions like Fibonacci series. 2. Some questions related to Perl Programming. 3. Some questions on state machine design. 4. Synthesizable and non synthesizable constructs in Verilog. 5. Be thorough with the stuff on the resume.
How would you verify a that a basic flip-flop works?
Technical Screening: Q: I was asked about basic programming questions like Leet Code (easy) but mostly based on array, hash-maps, strings and also resume discussion Full-Panel: Q: SystemVerilog constraints, fork-join, mailbox and semaphores based questions Q: Was asked to write scoreboard for a Asynchronous FIFO Q: Monitor and scoreboard code for an AXI write transaction (project based) Q: Resume based discussions Q: Some basic programming problems in language of preference
What is setup and hold time What is skew What is synchronous and asynchronous reset
Design a FSM to detect a certain sequence of numbers.
como voce se ve daqui 19 anos
basic digital design design ,pointers from c language ,basic verilog questions
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