Give a situation when your input made a difference in a project.
Design Verification Engineer Interview Questions
3,712 design verification engineer interview questions shared by candidates
How much of an improvement did your input make compared to the original decision? OR If there was compromises made, was the performance better or worse?
Technical questions and some logical Questions
1. Some simple random stimulus with specified constraints
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
how to generate 10 32 bit numbers that are all diffrent.
Q1: verification plan for a stated scenario
Have you ever had a conflict with a customer, how did you resolve it?
What do you expect to do when you work here?
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