Basic sv and uvm concepts
Design Verification Engineer Interview Questions
3,712 design verification engineer interview questions shared by candidates
1.what are the problems you faced during your project?
Why OOPs is important
OOP and polymorphism. Basic System Verilog and UVM coding.
3 Question 1 about one of my own projects, Question 2 about verification (Giving a situation which test would you run), Question 3 is a software question write a function that checks if the given input is a palindrome which is simple but then they start to make it harder and harder count how much palindromes there is in 1 string and now the same while getting the input 1 by 1 ... in O(nlogn) or O(n)
How to deal with clock domain crossing issues, timings in logic circuits etc
Convert the RTL logic to a gatelvel netlist. Constraint question from system verilog.
Write a complex asserino
Describe loading speed
round robin algorithm, scheduling? state diagram?
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