Given read and write freq, how to calculate FIFO depth?
Design Verification Engineer Interview Questions
3,710 design verification engineer interview questions shared by candidates
Write code for a UVC mimicing a memory . Reactive sequence in UVM
FIbonacci series
Most of the questions were about my projects and basic questions regarding them like UART, FIFO , basic digital design questions, System verilog questions
Computer Architecture, Logic Puzzles, SystemVerilog, C, Algorithms,Assembly
Basic question on UVM?
For the first screening round, all questions were based on out-of-order execution CPU. For the final interview, In 1st round, I was asked questions on out-of-order execution CPU 2nd round on cache and virtual memory 3rd round had one coding question based on queues and cache-related questions
Questions about UVM, computer architecture, C++ coding and background.
how to design a FSM using switch-case / shift register
We can make inputs randomly by flipping a coin why we dont do it?
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