About digital electronics for VLSI domain
Design Verification Engineer Interview Questions
3,710 design verification engineer interview questions shared by candidates
Why modport is used? What is polymorphism? What is deep copying ? what is inheritence? Why we are writing interface? Different Phases in UVM? Which phase are task and which are functions?
Questions about past experience with Verilog and VHDL
Basics of digital,. VLSI design etc
Basic SV/UVM questions
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Not Applicable and confidential as per norms
C++ encapsulation, inheritance and polymorphism
What is TLB cache? Why is it used?
MATLAB functions, DSP related questions;
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