expected salary with respect to your experience
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
I was asked if I had experience in obtaining authorizations, even though my resume reflected my experience in obtaining Retro authorizations, along with over a decade of experience in follow up/insurance verification in a hospital and professional setting.
To describe my previous work experience
What are the components used in an additional circuit?
Define performance?
Identify stress concentrations on a PCB
setup time, hold time, fifo, design of async/synch fifo
Interesting question about memory aliasing. You've two APIs write(addr, data) and read(addr, &data) just using these two APIs write an algorithm to identify one of the internal signals that has been shorted. You've no access to internal signals or the interface signals (black box verification)
Calculate fifo depth for following data rate Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s) Outgoing Data= 8 DATA/10 Clock. Burst size = 160
About work experience, Implement randc using rand, SV questions, Verilog design question, Fifo depth question, Scoreboard implementation of a design, MESI, Linked list traversing question. Looks like they need C++ even if the position requires SV/UVM only.
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