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Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
Shown a perl code, what does it do?
Coding: 1. The two-sum problem (famous DSA problem), both on sorted and unsorted arrays. 2. In an array, for each number, find out if it is greater than all the numbers to the right of it. Then questions about time and space complexity of my solution.
Puzzle: 2. There is a box with 13 W and 15 B balls. There are also 28 B balls on the outside. At each turn, two balls are randomly and simultaneously taken out of the box. If the balls are of different color, the W ball is returned to the box. If the balls are of the same color, they are removed and a B ball from outside is put into the box. After some turns, only one ball remains in the box. Can you deterministically tell the color of this ball?
Linked List traversal, Fibonacci algorithm (basic and recursive), the difference in complexity between the basic and recursive. Relatively straight forward. Second phone screen: "A person on a stairway needs to get from the bottom of the stairs to the top in the minimum number of steps, no, how possible combinations of steps, no, I don't think I explained that well...what if they took could only take one step forward for every"...really? is this even a real question? somehow the answer was yet again a Fibonacci sequence question. Next was reversing a singly linked list - oops, you can't use any references (!?), or another linked list.. Frustrating to have gotten the "B" team interviewer
setup time, hold time, fifo, design of async/synch fifo
Interesting question about memory aliasing. You've two APIs write(addr, data) and read(addr, &data) just using these two APIs write an algorithm to identify one of the internal signals that has been shorted. You've no access to internal signals or the interface signals (black box verification)
Calculate fifo depth for following data rate Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s) Outgoing Data= 8 DATA/10 Clock. Burst size = 160
About work experience, Implement randc using rand, SV questions, Verilog design question, Fifo depth question, Scoreboard implementation of a design, MESI, Linked list traversing question. Looks like they need C++ even if the position requires SV/UVM only.
Define performance?
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